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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
Introduction
Lattice’s Quad SPI-3 (System Packet Interface Level 3) to SPI-4 (System Packet Interface Level 4) Bridge is an IP
core which serves as a bridge between one SPI-4 and one to four SPI-3 links.
Lattice’s Quad SPI-3 to SPI-4 Bridge core is a core developed in conjunction with the Lattice ORCA ? ORSPI4
FPSC to provide a full solution. For more information on these and other Lattice products, refer to the Lattice web
site at www.latticesemi.com.
This user’s guide explains the functionality of the Quad SPI-3 to SPI-4 Bridge core and how it can be implemented
to provide a full SPI-3 to SPI-4 bridging solution. It also explains how to achieve the maximum level of performance.
The Quad SPI-3 to SPI-4 Bridge core comes with the documentation and the ?les listed below:
? Data sheet
? Lattice gate level netlist
? ModelSim simulation models and test benches available for free evaluation
? Core instantiation template
Features
? Quad full-featured SPI-3 LINK Interfaces as de?ned by the OIF speci?cations
? Supports full clock rates for SPI-3 core: 104MHz
? Each SPI-3 LINK can support up to eight ports
? Seamless integration with the SPI-4.2 Embedded core in the ORSPI4 FPSC
? 10Gbps aggregate throughput
? Parameterizable number of SPI-3 LINK interfaces (1 to 4)
? Parameterizable SPI-3 BYTE_MODE or PKT_MODE selection
? Con?gurable through MicroProcessor Interface (MPI) ORCA4 System Bus
? Programmable parity type on SPI-3 bus. Default is ODD.
General Description
The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the
ORCA ORSPI4 FPSC and provides a bridging function between one to four SPI-3 links and a SPI-4 link.
The ORSPI4 is an FPSC built on the Series 4 re-con?gurable embedded System-on-a-Chip (SoC) architecture and
intended for high-speed data transmission. The SPI-4.2 interface block provides a 10Gbps physical to Link Layer
interfaces in conformance to the OIF-SPI4-02.0 speci?cation and bi-directional interfaces with an aggregate band-
width of 13.6Gbps.
SPI-4 is an interface for packet and cell transfer between a Physical Layer (PHY) device and a Link Layer device,
for applications such as OC-192 ATM and Packet over SONET/SDH (POS), as well as 10Gbps Ethernet applica-
tions.
The SPI-3 interface de?nes the interface between Physical Layer and Link Layer devices, and can be used to
implement several packet-based protocols. The SPI-3 interface supports clock transfer rates of 104MHz and an
aggregate bit rate of 2.5Gbps with a 32-bit wide bus.
The Quad SPI-3 to SPI-4 Bridge IP core is provided with implementation scripts, test benches and documentation
to allow designers to bridge multiple 2.5Gbps ports (SPI-3) to a 10Gbps (SPI-4) pipe.
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